With the purpose of improving the performance of semiconductor devices or reducing the manufacturing costs, higher-density integration of semiconductor devices is in progress. In order to realize the higher-density integration of semiconductor devices, improvement of lithography technology is necessary. Lithography is a technique for patterning a mask for a circuit pattern in photosensitive resin (hereinafter referred to as resist) applied onto a silicon wafer by the use of an exposure apparatus. The trend toward finer dimensions in lithography has been maintained by improvements of exposure technology and resist materials.
However, in recent years, higher densities of circuit patterns are further in progress. For example, patterning with a half pitch of 32 nm is necessitated. Therefore, a patterning technique different from the prior art is indispensable. Accordingly, double patterning techniques are being developed. In the double patterning technology, one layer of circuit pattern is divided into plural (e.g., two) circuit patterns of lower circuit pattern density, and their respective masks are prepared. Using these masks, patterning is successively performed on the same region on a silicon wafer. Consequently, plural circuit patterns are successively generated in the same region on the silicon wafer. The plural circuit patterns are joined together at a joint portion and a microscopic circuit pattern of high density is fabricated.
When the double patterning technology is used, a joint portion is always formed between the circuit patterns. A deviation of the joint portion greatly affects the wafer fabrication yield. Therefore, semiconductor measuring apparatus and inspection apparatus are required to measure the amount of deviation of the joint portion between the circuit patterns or evaluate the shape of the joint portion of the pattern and to make an accurate decision as to whether the two patterns have been normally coupled together. Especially, pattern joint portions are formed in large amounts on wafers. Therefore, the shapes of the pattern joint portions are required to be evaluated efficiently by a simple method.
Methods described in Patent literatures 1-4 are available as methods used for evaluation of the shapes of the pattern joint portions. In a common manner to these methods, a shot image of a pattern to be evaluated and a pattern shape (hereinafter referred to as the reference pattern) produced in a case where the pattern is normally formed are compared, and a portion of different shape is detected as a defect. As the reference pattern, a design pattern corresponding to the pattern to be inspected or a good-quality pattern fabricated on the wafer is used.